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| 1 mx25l1606e 3v, 16m-bit [x 1/x 2] cmos serial flash memory key features ? hold feature ? low power consumption ? auto erase and auto program algorithms ? additional 512 bit secured otp for unique identifer p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e
2 contents features .................................................................................................................................................................. 5 general description ......................................................................................................................................... 6 pin configurations ............................................................................................................................................. 7 pin description ...................................................................................................................................................... 8 block diagram ....................................................................................................................................................... 9 memory organization ....................................................................................................................................... 10 table 1. memory organization ..... ..................................................................................................................... 10 device operation ................................................................................................................................................ 11 figure 1. serial modes supported ...................................................................................................................... 11 data protection .................................................................................................................................................. 12 table 2. protected area sizes ............................................................................................................................ 13 table 3. 512 bit secured otp defnition ........................................................................................................... 14 hold feature ........................................................................................................................................................ 15 figure 2. hold condition operation ...... ............................................................................................................. 15 command description ....................................................................................................................................... 16 table 4. command definition ..................................................................................................................... 16 (1) write enable (wren) ... ................................................................................................................................ 17 (2) write disable (wrdi) .................................................................................................................................... 17 (3) read status register (rdsr) ...................................................................................................................... 17 (4) write status register (wrsr) ...................................................................................................................... 18 table 5. protection modes .................................................................................................................................. 19 (5) read data bytes (read) ..... ........................................................................................................................ 20 (6) read data bytes at higher speed (fast_read) ..... .................................................................................. 20 (7) dual output mode (dread) ...... ................................................................................................................... 20 (8) sector erase (se) ......................................................................................................................................... 20 (9) block erase (be) ........................................................................................................................................... 21 (10) chip erase (ce) ...... .................................................................................................................................... 21 (11) page program (pp) ..................................................................................................................................... 21 (12) deep power-down (dp) ... ........................................................................................................................... 22 (13) release from deep power-down (rdp), read electronic signature (res) ............................................. 22 (14) read identifcation (rdid) .......................................................................................................................... 23 (15) read electronic manufacturer id & device id (rems) ... ........................................................................... 23 table 6. id definitions ................................................................................................................................. 23 (16) enter secured otp (enso) ....................................................................................................................... 23 (17) exit secured otp (exso) .......................................................................................................................... 23 (18) read security register (rdscur) ............................................................................................................ 24 table 7. security register definition ...... ............................................................................................. 24 (19) write security register (wrscur) ............................................................................................................ 24 p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 3 (20) read sfdp mode (rdsfdp) ..................................................................................................................... 25 figure 3. read serial flash discoverable parameter (rdsfdp) sequence ...... ............................................... 25 table 8. signature and parameter identifcation data values ........................................................................... 26 table 9. parameter table (0): jedec flash parameter tables ...... ................................................................... 27 table 10. parameter table (1): macronix flash parameter tables .................................................................... 29 power-on state ................................................................................................................................................... 31 electrical specifications .............................................................................................................................. 32 absolute maximum ratings ... .................................................................................................................. 32 figure 4. maximum negative overshoot waveform .......................................................................................... 32 capacitance ta = 25 c, f = 1.0 mhz ............................................................................................................. 32 figure 5. maximum positive overshoot waveform ............................................................................................ 32 figure 6. input test waveforms and measurement level .............................................................. 33 figure 7. output loading ........................................................................................................................... 33 table 11. dc characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v - 3.6v) ... 34 table 12. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v - 3.6v) ... 35 timing analysis ........................................................................................................................................................ 36 figure 8. serial input timing ..... ......................................................................................................................... 36 figure 9. output timing ...... ................................................................................................................................ 36 figure 10. hold timing ....................................................................................................................................... 37 figure 11. wp# disable setup and hold timing during wrsr when srwd=1 ................................................ 37 figure 12. write enable (wren) sequence (command 06) ............................................................................. 38 figure 13. write disable (wrdi) sequence (command 04) .............................................................................. 38 figure 14. read status register (rdsr) sequence (command 05) ................................................................ 39 figure 15. write status register (wrsr) sequence (command 01) ............................................................... 39 figure 16. read data bytes (read) sequence (command 03) ..... ................................................................. 39 figure 17. read at higher speed (fast_read) sequence (command 0b) ................................................... 40 figure 18. dual output read mode sequence (command 3b) ...... ................................................................... 41 figure 19. sector erase (se) sequence (command 20) .................................................................................. 41 figure 20. block erase (be) sequence (command 52 or d8) ...... .................................................................... 41 figure 21. chip erase (ce) sequence (command 60 or c7) ........................................................................... 42 figure 22. page program (pp) sequence (command 02) ...... .......................................................................... 42 figure 23. deep power-down (dp) sequence (command b9) ...... .................................................................. 43 figure 24. release from deep power-down (rdp) sequence (command ab) ..... .......................................... 43 figure 25. read electronic signature (res) sequence (command ab) .......................................................... 43 figure 26. read identifcation (rdid) sequence (command 9f) ...................................................................... 44 figure 27. read electronic manufacturer & device id (rems) sequence (command 90) .............................. 44 figure 28. read security register (rdscur) sequence (command 2b) ........................................................ 45 figure 29. write security register (wrscur) sequence (command 2f) ....................................................... 45 figure 30. power-up timing ............................................................................................................................... 46 table 13. power-up timing ............................................................................................................................... 46 p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 4 operating conditions ....................................................................................................................................... 47 figure 31. ac timing at device power-up ...... ................................................................................................... 47 figure 32. power-down sequence ..... ............................................................................................................... 48 erase and programming performance .................................................................................................... 49 data retention .................................................................................................................................................... 49 latch-up characteristics .............................................................................................................................. 49 ordering information ...................................................................................................................................... 50 part name description ..................................................................................................................................... 51 package information ........................................................................................................................................ 52 16-pin sop (300mil) .......................................................................................................................................... 52 8-pin sop (150mil) ............................................................................................................................................ 53 8-pin sop (200mil) ............................................................................................................................................ 54 8-pin pdip (300mil) ........................................................................................................................................... 55 8-land wson (6x5mm) ................................................................................................................................... 56 8-land uson (4x4mm) ... ................................................................................................................................. 57 24-ball bga ..................................................................................................................................................... 58 revision history ................................................................................................................................................. 59 p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 5 16m-bit [x 1 / x 2] cmos serial flash features general ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program opera - tions ? supports serial peripheral interface -- mode 0 and mode 3 ? 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (dual output mode) structure ? 512 equal sectors with 4k byte each - any sector can be erased individually ? 32 equal blocks with 64k byte each - any block can be erased individually ? program capability - byte base - page base (256 bytes) ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance - fast access time: 86mhz serial clock - serial clock of dual output mode : 80mhz - fast program time: 0.6ms(typ.) and 3ms(max.)/page - byte program time: 9us (typ.) - fast erase ti me: 40ms(typ.) /sector ; 0.4s(typ.) /block ? low power consumption - low active read current: 25ma(max.) at 86mhz - low active programming current: 15ma (typ.) - low active sector erase current: 9ma (typ.) - low standby current: 15ua (typ.) - deep power-down mode 2ua (typ.) ? typical 100,000 erase/program cycles ? 20 years of data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp3-bp0 status bit defnes the size of the area to be software protection against program and erase instructions - additional 512 bit secured otp for unique identifer ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector - automatically programs and verifes data at select - ed page by an internal algorithm that automatically times the program pulse widths (any page to be pro - gramed should have page in the erased state frst) ? status register feature ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems commands for 1-byte manufacturer id and 1-byte device id ? support serial flash discoverable parameters (sfdp) mode hardware features ? package - 16-pin sop (300mil) - 8-pin sop (150mil) - 8-pin sop (200mil) - 8-pin pdip (300mil) - 8-land wson (6x5mm) - 8-land uson (4x4mm) - 24-ball bga - all devices are rohs compliant and halogen- free p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 6 general description the device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in dual output read mode, the si and so pins become sio0 and sio1 pins for data output. the device provides sequential read operation on the whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fed page or sector/block locations will be executed. program command is executed on byte basis, or page basis, or word basis. erase command is executed on sector, or block, or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode. the device utilizes macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 7 pin configurations 16-pin sop (300mil) 8-land wson (6x5mm), uson (4x4mm) 8-pin sop (200mil, 150mil) 1 2 3 4 5 6 7 8 hold# vcc nc nc nc nc cs# so/sio1 16 15 14 13 12 11 10 9 sclk si/sio0 nc nc nc nc gnd wp# 1 2 3 4 cs# so/sio1 wp# gnd vcc hold# sclk si/sio0 8 7 6 5 1 2 3 4 cs# so/sio1 wp# gnd 8 7 6 5 vcc hold# sclk si/sio0 1 2 3 4 cs# so/sio1 wp# gnd 8 7 6 5 vcc hold# sclk si/sio0 8-pin pdip (300mil) 24-ball bga nc vcc wp# hold# nc nc gnd nc si/sio0 nc nc sclk so/sio1 nc nc nc nc nc nc a b c d e 5 4 3 2 1 cs# nc nc nc nc p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 8 symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for dual output mode) so/sio1 serial data output (for 1 x i/o)/ serial data output (for dual output mode) sclk clock input wp# write protection hold# hold, to pause the device without deselecting the device vcc + 3.3v power supply gnd ground pin description p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 9 block diagram address generator memory array y-decoder x-decoder data register sram buffer si/sio0 so/sio1 sio2 * sio3 * wp# * hold# * reset# * cs# sclk clock generator state machine mode logic sense amplifier hv generator output buffer * depends on part number options. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 10 memory organization table 1. memory organization block sector address range 31 511 1ff000h 1fffffh : : : 496 1f0000h 1f0fffh 30 495 1ef000h 1effffh : : : 480 1e0000h 1e0fffh : : : : : : : : 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 11 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next cs# falling edge. in standby mode, so pin of the device is high-z. the cs# falling time needs to follow tchcl spec. 3. when correct command is inputted to this device, it enters active mode and remains in active mode until next cs# rising edge. the cs# rising time needs to follow tclch spec. 4. input data is latched on the rising edge of serial clock(sclk) and data is shifted out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown in "figure 1. serial modes supported" . 5. for the following instructions:rdid, rdsr, rdscur, read, fast_read, rdsfdp, dread, res, and rems the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, rdp, dp, enso, exso,and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. while a w rite status register, program, or erase operation is in progress, access to the memory array is ne - glected and will not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 12 data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise . ? v alid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - w rite disable (wrdi) command completion - w rite status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) comma nd completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic sig - nature command (res). ? advanced security features: there are some protection and security features which protect content from inad - vertent write and hostile access. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 13 table 2. protected area sizes status bit protect level bp3 bp2 bp1 bp0 mx25l1606e 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 31 st ) 0 0 1 0 2 (2blocks, block 30 th -31 st ) 0 0 1 1 3 (4blocks, block 28 th -31 st ) 0 1 0 0 4 (8blocks, block 24 th -31 st ) 0 1 0 1 5 (16blocks, block 16 th -31 st ) 0 1 1 0 6 (32blocks, all) 0 1 1 1 7 (32blocks, all) 1 0 0 0 8 (32blocks, all) 1 0 0 1 9 (32blocks, all) 1 0 1 0 10 (16blocks, block 0 th -15 th ) 1 0 1 1 11 (24blocks, block 0 th -23 rd ) 1 1 0 0 12 (28blocks, block 0 th -27 th ) 1 1 0 1 13 (30blocks, block 0 th -29 th ) 1 1 1 0 14 (31blocks, block 0 th -30 th ) 1 1 1 1 15 (32blocks, all) i. block lock protection - the software protected mode (spm): mx25l1606e: use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only . the proe - cted area defnition is shown as "table 2. protected area sizes" , the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to "table 2. protected area sizes" . - the hardware proteced mode (hpm) uses wp# to protect the mx25l1606e: bp3-bp0 bits and srwd bit. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 14 ii. additional 512 bit secured otp for unique identifer: to provide 512 bit one-time program area for setting device unique serial number - which may be set by factory or system customer. please refer to "table 3. 512 bit secured otp defnition" . - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 512 bit secured otp by entering 512 bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 512 bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to "table 7. security register defini - tion" for security register bit defnition and "table 3. 512 bit secured otp defnition" for address range def - nition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 512 bit se - cured otp mode, array access is not allowed. 7deohelw6hfxuhg273'hqlwlrq address range size standard factory lock customer lock xxxx00~xxxx0f 128-bit esn (electrical serial number) determined by customer xxxx10~xxxx3f 384-bit n/a p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 15 hold feature hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select (cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock(sclk) signal is being low (if serial clock signal is not being low, hold operation will not end until serial clock being low). figure 2. hold condition operation valid data valid data valid data don?t care high_z high_z don?t care bit 7 bit 6 bit 5 bit 5 bit 7 bit 7 bit 6 bit 6 hold# cs# sclk si/sio0 so/sio1 (internal) so/sio1 (external) valid data valid data valid data don?t care high_z high_z don?t care bit 7 bit 6 bit 5 bit 3 bit 4 bit 7 bit 6 bit 4 bit 5 bit 3 hold# cs# sclk si/sio0 so/sio1 (internal) so/sio1 (external) during the hold operation, the serial data output (so) is high impedance when hold# pin goes low and will keep high impedance until hold# pin goes high and sclk goes low . the serial data input (si) is don't care if both serial clock (sclk) and hold# pin goes low and will keep the state until sclk goes low and hold# pin goes high. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communica - tion with chip, the hold# must be at high and cs# must be at low. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 16 table 4. command definition command (byte) wren (write enable) wrdi (write disable) wrsr (write status register) rdid (read identifc- ation) rdsr (read status register) read (read data) fast read (fast read data) 1 st byte 06 (hex) 04 (hex) 01 (hex) 9f (hex) 05 (hex) 03 (hex) 0b (hex) 2 nd byte ad1 ad1 3 rd byte ad2 ad2 4 th byte ad3 ad3 5 th byte dummy action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to write new values to the status register outputs jedec id: 1-byte manufact-urer id & 2-byte device id to read out the values of the status register n bytes read out until cs# goes high n bytes read out until cs# goes high command (byte) rdsfdp (read sfdp) res (read electronic id) rems (read electronic manufacturer & device id) dread (double output mode command) se (sector erase) be (block erase) ce (chip erase) 1 st byte 5a (hex) ab (hex) 90 (hex) 3b (hex) 20 (hex) 52 or d8 (hex) 60 or c7 (hex) 2 nd byte ad1 x x ad1 ad1 ad1 3 rd byte ad2 x x ad2 ad2 ad2 4 th byte ad3 x add (note 1) ad3 ad3 ad3 5 th byte dummy dummy action read sfdp mode to read out 1-byte device id output the manufacturer id & device id n bytes read out by dual output until cs# goes high to erase the selected sector to erase the selected block to erase whole chip command (byte) pp (page program) rdscur (read security register) wrscur (write security register) enso (enter secured otp) exso (exit secured otp) dp (deep power down) rdp (release from deep power down) 1 st byte 02 (hex) 2b (hex) 2f (hex) b1 (hex) c1 (hex) b9 (hex) ab (hex) 2 nd byte ad1 3 rd byte ad2 4 th byte ad3 5 th byte action to program the selected page to read value of security register to set the lock-down bit as "1" (once lock-down, cannot be updated) to enter the 512 bit secured otp mode to exit the 512 bit secured otp mode enters deep power down mode release from deep power down mode note 1: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 2: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hidden mode. command description p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 17 (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren in - struction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction code cs# goes high. the sequence is shown as "figure 12. write enable (wren) sequence (command 06)" . (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low sending wrdi instruction code cs# goes high. the sequence is shown as "figure 13. write disable (wrdi) sequence (command 04)" . the wel bit is reset by following situations: - power-up - w rite disable (wrdi) instruction completion - w rite status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion (3) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. the sequence is shown as "figure 14. read status register (rdsr) sequence (command 05)" . the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. the program/erase command will be ignored and not affect value of wel bit if it is applied to a protected memory area. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 18 bp3, bp2, bp1, bp0 bits. the block protect (bp3-bp0) bits, non-volatile bits, indicate the protected area(as de - fned in "table 2. protected area sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3-bp0) bits requires the write status register (wrsr) in - struction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase(ce) instructions (only if all block protect bits set to 0, the ce instruc - tion can be executed). srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp# pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3-bp0) are read only. (4) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp3-bp0) bits to defne the protected area of memory (as shown in "table 2. protected area sizes" ). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal (please refer to "figure 11. wp# disable setup and hold timing during wrsr when srwd=1" ). the wrsr instruction cannot be executed once the hard - ware protected mode (hpm) is entered. the wrsr instruction has no effect on b6, b1, b0 of the status register. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on si cs# goes high. the sequence is shown as "figure 15. write status register (wrsr) sequence (command 01)" . the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. status register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) 0 bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 0 (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit 0 non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit note 1: please refer to "table 2. protected area sizes" . p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 19 table 5. protection modes note: as defned by the values in the block protect (bp3-bp0) bits of the status register, as shown in "table 2. protected area sizes" . as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when sr wd bit=0, no matter wp# is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3-bp0. the protected area, which is defned by bp3-bp0 is at software protected mode (spm). - when sr wd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp3-bp0. the protected area, which is defned by bp3-bp0, is at software protected mode (spm) note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when sr wd bit=1, and then wp# is low (or wp# is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3-bp0 and hardware protected mode by the wp# to against data modifcation. note: to exit the hardware protected mode requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3-bp0. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp3-bp0 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp3-bp0 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 20 (5) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code3-byte address on si data out on so to end read operation can use cs# to high at any time during data out. the sequence is shown as "figure 16. read data bytes (read) sequence (command 03)" . (6) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end f ast_read operation can use cs# to high at any time during data out. the sequence is shown as "figure 17. read at higher speed (fast_ read) sequence (command 0b)" . while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (7) dual output mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 1i/2o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing dread instruction is: cs# goes low sending dread instruction 3-byte address on si 8-bit dummy cycle data out interleave on sio1 & sio0 to end dread operation can use cs# to high at any time during data out. the sequence is shown as "figure 18. dual output read mode sequence (command 3b)" . while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. the dread only perform read operation. program/erase /read id/read status....operation do not support dread throughputs. (8) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 21 sending the sector erase (se). any address of the sector (see "table 1. memory organization" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of the address been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. the sequence is shown as "figure 19. sector erase (se) sequence (command 20)" . the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets during the tse tim - ing, and clears when sector erase cycle is completed, and the write enable latch (wel) bit is cleared. if the page is protected by bp3-bp0 bits, the sector erase (se) instruction will not be executed on the page. (9) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte sector erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see "table 1. memory organiza - tion" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. the sequence is shown as "figure 20. block erase (be) sequence (command 52 or d8)" . the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets during the tbe tim - ing, and clears when sector erase cycle is completed, and the write enable latch (wel) bit is cleared. if the page is protected by bp3-bp0 bits, the block erase (be) instruction will not be executed on the page. (10) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must be executed to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see "table 1. memory organization" ) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low sending ce instruction code cs# goes high. the sequence is shown as "figure 21. chip erase (ce) sequence (command 60 or c7)" . the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be checked while the chip erase cycle is in progress. the wip sets during the tce tim - ing, and clears when chip erase cycle is completed, and the write enable latch (wel) bit is cleared. if the chip is protected by bp3-bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3- bp0 all set to "0". (11) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the eight least signifcant address p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 22 bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the requested page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. the sequence is shown as "figure 22. page program (pp) se - quence (command 02)" . the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the page program cycle is in progress. the wip sets during the tpp timing, and clears when page program cycle is completed, and the write enable latch (wel) bit is cleared. if the page is protected by bp3-bp0 bits, the page program (pp) instruction will not be executed. (12) deep power-down (dp) the deep power-down (dp) instruction is for setting the device to minimum power consumption (the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to en - ter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, the device is in standby mode, not deep power-down mode. the sequence of issuing dp instruction is: cs# goes low sending dp instruction code cs# goes high. the se - quence is shown as "figure 23. deep power-down (dp) sequence (command b9)" . once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (13) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is completed by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip se - lect (cs#) must remain high for at least tres2(max), as specifed in "table 12. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v - 3.6v)" . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as "table 6. id definitions" . this is not the same as rdid instruction. it is not recommended to use for new design. for new de - sign, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be ex - ecuted, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/ erase/write cycle in progress. the sequence is shown in "figure 24. release from deep power-down (rdp) sequence (command ab)" and "fig- ure 25. read electronic signature (res) sequence (command ab)" . the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 23 deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is for releasing from deep power down mode. (14) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id and device id are listed as "table 6. id definitions" . the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code 24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. the sequence is shown as "figure 26. read identifcation (rdid) sequence (command 9f)" . while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. (15) read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initi - ated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes ad - dress (a7~a0). after which, the manufacturer id for macronix and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in "figure 27. read electronic manufacturer & device id (rems) sequence (command 90)" . the device id values are listed in "table 6. id definitions" . if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufac - turer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table 6. id definitions command type mx25l1606e rdid command manufacturer id memory type memory density c2 20 15 res command electronic id 14 rems manufacturer id device id c2 14 (16) enter secured otp (enso) the enso instruction is for entering the additional 512 bit secured otp mode. while the device is in 512 bit se - cured otp mode, array access is not available. the additional 512 bit secured otp is independent from main array, and may be used to store unique serial number for system identifer. after entering the secured otp mode, follow standard read or program procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once se - curity otp is lock down, only read related commands are valid. (17) exit secured otp (exso) p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 24 (18) read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low sending rdscur instruction security register data out on so cs# goes high. the sequence is shown as "figure 28. read security register (rdscur) sequence (command 2b)" . the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for custom - er lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 512 bit secured otp area cannot be updated any more. table 7. security register definition (19) write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 512 bit secured otp area. once the ldso bit is set to "1", the se - cured otp area cannot be updated any more. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. the sequence is shown as "figure 29. write security register (wrscur) sequence (command 2f)" . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x ldso (indicate if lock-down) secured otp indicator bit reserved reserved reserved reserved reserved reserved 0 = not lockdown 1 = lock-down (cannot program/erase otp) 0 = nonfactory lock 1 = factory lock volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit the exso instruction is for exiting the additional 512 bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 25 (20) read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a standard of jedec. jesd216. v1.0. figure 3. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 26 table 8. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh sfdp table below is for mx25l1606em2i-12g, MX25L1606EM1I-12G, mx25l1606emi-12g, mx25l1606epi- 12g, mx25l1606ezni-12g, mx25l1606ezui-12g and mx25l1606exci-12g p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 27 table 9. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111 b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 1b 81h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 0b (1-4-4) fast read 0=not support 1=support 21 0b (1-1-4) fast read 0=not support 1=support 22 0b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 00ff ffff h (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0000 b 00h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 000b (1-4-4) fast read opcode 39h 15:08 ff h ffh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 0000 b 00h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 ffh ffh sfdp table below is for mx25l1606em2i-12g, MX25L1606EM1I-12G, mx25l1606emi-12g, mx25l1606epi- 12g, mx25l1606ezni-12g, mx25l1606ezui-12g and mx25l1606exci-12g p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 28 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ch 04:00 0 1000 b 08h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 3bh 3bh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3eh 20:16 0 0000 b 00h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-2-2) fast read opcode 3fh 31:24 ffh ffh (2-2-2) fast read 0=not support 1=support 40h 00 0b eeh unused 03:01 111 b (4-4-4) fast read 0=not support 1=support 04 0b unused 07:05 111 b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 46h 20:16 0 0000 b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 4ah 20:16 0 0000 b 00h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (4-4-4) fast read opcode 4bh 31:24 ffh ffh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 10h 10h sector type 2 erase opcode 4fh 31:24 d8h d8h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 00h 00h sector type 3 erase opcode 51h 15:08 ffh ffh sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh sfdp table below is for mx25l1606em2i-12g, MX25L1606EM1I-12G, mx25l1606emi-12g, mx25l1606epi- 12g, mx25l1606ezni-12g, mx25l1606ezui-12g and mx25l1606exci-12g p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 29 table 10. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 36h 00h 36h vcc supply minimum voltage 1650h=1.650v, 1750h=1.750v 2250h=2.250v, 2350h=2.350v 2650h=2.650v, 2700h=2.700v 63h:62h 23:16 31:24 00h 27h 00h 27h h/w reset# pin 0=not support 1=support 65h:64h 00 0b 4ff6h h/w hold# pin 0=not support 1=support 01 1b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 0b s/w reset opcode reset enable (66h) should be issued before reset opcode 11:04 1111 1111 b (ffh) program suspend/resume 0=not support 1=support 12 0b erase suspend/resume 0=not support 1=support 13 0b unused 14 1b wrap-around read mode 0=not support 1=support 15 0b wrap-around read mode opcode 66h 23:16 ffh ffh wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 ffh ffh individual block lock 0=not support 1=support 6bh:68h 00 0b cffeh individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 1b individual block lock opcode 09:02 1111 1111 b (ff h) individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 1b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11 b unused 31:16 ffh ffh unused 6fh:6ch 31:00 ffh ffh mx25l1606em2i-12g-sfdp_2014-10-14 sfdp table below is for mx25l1606em2i-12g, MX25L1606EM1I-12G, mx25l1606emi-12g, mx25l1606epi- 12g, mx25l1606ezni-12g, mx25l1606ezui-12g and mx25l1606exci-12g p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 30 note 1: h/b is hexadecimal or binary . note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch, 32kb=2^0fh, 64kb=2^10h note 6: all unused and undefned area data is blank ffh for sfdp tables that are defned in parameter identifcation header. all other areas beyond defned sfdp table are reserved by macronix. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 31 power-on state the device is at the following states after power-up: - standby mode (please n ote it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage until the vcc reaches the following levels: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to "figure 30. power-up timing" . note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed.(generally around 0.1uf) initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 32 notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained w ithin the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see "figure 4. maximum negative overshoot waveform" and "figure 5. maximum positive overshoot waveform" . absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v figure 4. maximum negative overshoot waveform figure 5. maximum positive overshoot waveform vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns rating value ambient operating temperature industrial grade -40 c to 85 c storage temperature -55c to 125c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 33 figure 6. input test waveforms and measurement level figure 7. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf/15pf including jig capacitance p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 34 table 11. dc characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v - 3.6v) symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 15 25 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 2 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 25 ma f=86mhz ft=80mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 1 20 ma f=66mhz, sclk=0.1vcc/0.9vcc, so=open 1 10 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 15 20 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 1 3 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 9 20 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 15 20 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua notes: 1. t ypical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. not 100% tested. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 35 table 12. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v - 3.6v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr dc 86 mhz frsclk fr clock frequency for read instructions dc 33 mhz ftsclk ft clock frequency for dread instructions dc 80 mhz tch (1) tclh clock high time fc=86mhz 5.5 ns fr=33mhz 13 ns tcl (1) tcll clock low time fc=86mhz 5.5 ns fr=33mhz 13 ns tclch (2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl (2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl tcsh cs# deselect time read 15 ns write 40 ns tshqz (2) tdis output disable time 6 ns tclqv tv clock low to output valid, loading 30pf/15pf 8/6 ns tclqx tho output hold time 0 ns thlch hold# setup time (relative to sclk) 5 ns tchhh hold# hold time (relative to sclk) 5 ns thhch hold setup time (relative to sclk) 5 ns tchhl hold hold time (relative to sclk) 5 ns thhqx (2) tlz hold to output low-z 6 ns thlqz (2) thz hold# to output high-z 6 ns twhsl (4) write protect setup time 20 ns tshwl (4) write protect hold time 100 ns tdp (2) cs# high to deep power-down mode 10 us tres1 (2) cs# high to standby mode without electronic signature read 8.8 us tres2 (2) cs# high to standby mode with electronic signature read 8.8 us tw write status register cycle time 5 40 ms tbp byte-program 9 50 us tpp page program cycle time 0.6 3 ms tse sector erase cycle time 40 200 ms tbe block erase cycle time 0.4 2 s tce chip erase cycle time 6.5 20 s notes: 1. tch + tcl must be greater than or equal to 1/ fc. for fast read, tcl/tch=5.5/5.5. 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as "figure 6. input test waveforms and measurement level" & "figure 7. output loading" . 6. the cs# rising time needs to follow tclch spec and cs# falling time needs to follow tchcl spec. p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 36 figure 8. serial input timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 9. output timing lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si timing analysis p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 37 figure 10. hold timing tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# * si is "don't care" during hold operation. figure 11. wp# disable setup and hold timing during wrsr when srwd=1 high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 38 figure 12. write enable (wren) sequence (command 06) figure 13. write disable (wrdi) sequence (command 04) 21 34567 high-z 0 06 command sclk si cs# so 21 34567 high-z 0 04 command sclk si cs# so p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 39 figure 14. read status register (rdsr) sequence (command 05) figure 15. write status register (wrsr) sequence (command 01) figure 16. read data bytes (read) sequence (command 03) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 21 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 40 figure 17. read at higher speed (fast_read) sequence (command 0b) 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0b command p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 41 figure 18. dual output read mode sequence (command 3b) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 30 31 32 3b(hex) dummy address bit23, bit22, bit21...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 39 40 41 42 43 8 bit instruction 24 bit address 8 dummy cycle data output figure 19. sector erase (se) sequence (command 20) figure 20. block erase (be) sequence (command 52 or d8) note: se command is 20(hex). note: be command is 52 or d8(hex). 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52 or d8 command 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 42 figure 21. chip erase (ce) sequence (command 60 or c7) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command figure 22. page program (pp) sequence (command 02) note: ce command is 60(hex) or c7(hex). 21 34567 0 60 or c7 sclk si cs# command p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 43 figure 23. deep power-down (dp) sequence (command b9) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command figure 24. release from deep power-down (rdp) sequence (command ab) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command figure 25. read electronic signature (res) sequence (command ab) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 44 notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst (2) instruction is 90(hex). figure 26. read identifcation (rdid) sequence (command 9f) 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so 90 high-z command figure 27. read electronic manufacturer & device id (rems) sequence (command 90) 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 45 figure 28. read security register (rdscur) sequence (command 2b) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 security register out security register out high-z msb 7 6543210 msb 7 sclk si cs# so 2b figure 29. write security register (wrscur) sequence (command 2f) 21 34567 0 2f sclk si cs# command so high-z p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 46 figure 30. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. symbol parameter min. max. unit tvsl (1) vcc(min) to cs# low 200 us note: 1. the parameter is characterized only. table 13. power-up timing p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 47 operating conditions at device power-up and power-down ac timing illustrated in "figure 31. ac timing at device power-up" and "figure 32. power-down sequence" are the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ignored, the device will not operate correctly. during power-up and power down, cs# need to follow the voltage applied on vcc to keep the device not be se - lected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "table 12. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v - 3.6v)" . symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd figure 31. ac timing at device power-up p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 48 figure 32. power-down sequence during power down, cs# need to follow the voltage drop on vcc to avoid mis-operation. cs# sclk vcc p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 49 erase and programming performance note: 1. t ypical program and erase time assumes the following conditions: 25 c, 3.3v, and checkerboard pattern. 2. under worst conditions of 85 c and 2.7v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. 4. erase/program cycles comply with jedec: jesd-47 & jesd22-a1 17 standard. min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics parameter min. typ. (1) max. (2) unit write status register time 5 40 ms sector erase time 40 200 ms block erase time 0.4 2 s chip erase time 6.5 20 s byte program time (via page program command) 9 50 us page program time 0.6 3 ms erase/program cycle 100,000 cycles data retention parameter condition min. max. unit data retention 55?c 20 years p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 50 ordering information part no. clock (mhz) temperature package remark mx25l1606emi-12g 86 -40 c~85 c 16-sop (300mil) rohs compliant MX25L1606EM1I-12G 86 -40 c~85 c 8-sop (150mil) rohs compliant mx25l1606em2i-12g 86 -40 c~85 c 8-sop (200mil) rohs compliant mx25l1606epi-12g 86 -40 c~85 c 8-pdip (300mil) rohs compliant mx25l1606ezni-12g 86 -40 c~85 c 8-wson (6x5mm) rohs compliant mx25l1606ezui-12g 86 -40 c~85 c 8-uson (4x4mm) rohs compliant mx25l1606exci-12g 86 -40 c~85 c 24-ball bga rohs compliant p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 51 part name description mx 25 l 12 zn i g option: g: rohs compliant and halogen-free speed: 12: 86mhz temperature range: i: industrial (-40c to 85c) package: zn: wson (0.8mm package height) zu: uson (0.6mm package height) m: 300mil 16-sop m1: 150mil 8-sop m2: 200mil 8-sop p: 300mil 8-pdip xc: 24-ball bga density & mode: 1606e: 16mb type: l: 3v device: 25: serial flash 1606e p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 52 package information 16-pin sop (300mil) p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 53 8-pin sop (150mil) p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 54 8-pin sop (200mil) p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 55 8-pin pdip (300mil) p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 56 8-land wson (6x5mm) p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 57 8-land uson (4x4mm) p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 58 24-ball bga p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 59 revision history revision no. description page date 0.01 1. document status: changed from advanced information to preliminary p5 jan/28/2010 2. table 2. protected area sizes: modifed content p12 3. da ta protection-block lock protection: revised description p1 1 4. table 4. command description: modifed rddmc p15 5. performance: revised low power consumption (low active read p5,31 current and low standby current) 1.0 1. removed "preliminary" p5 mar/30/2010 2. general description: revision p6 3. command description: dmc parameter id table (2) revision p26 4. changed is b1(max.) from 50ua to 25ua p5,30,45 5. modifed figure 28. ac timing at device power-up p42 6. added figure 29 p43 7. modifed " dual output mode (dread)" description p19 8. modifed fc, fr, ft/(min.) from 10khz to dc p31 9. revised dmc description p24 1.1 1. modifed figure 19. block erase (be) sequence p37 ma y/19/2010 2. modifed rems description p22,40 3. modifed figure 8. output timing p32 4. revised vcc supply minimum voltage address bits p25 5. revised note 4 of erase and programming performance table p44 6. changed wording from dmc to sfdp p6,10,15,24 7. revised sfdp sequence description p24 1.2 1. removed sfdp sequence description & content table p6,10,15, jul/02/2010 p24 1.3 1. added rdscur & wrscur diagram form p38 sep/01/201 1 2. added cs# rising and falling time description p10,28 3. modifed tw from 40(typ.)/100(max.) to 5(typ.)/40(max.) p28,42 4. modifed description for rohs compliance p6,43,44 5. removed mx25l8006e content (to a separated datasheet) 1.4 1. added read sfdp (rdsfdp) mode p6,1 1,16, feb/23/2012 p25~30,35 2. added 24-ball bga package information p6,7,50,51, p58 1.5 1. updated parameters for dc/ac characteristics p5,34,35 nov/06/2013 2. updated erase and programming performance p5,49 1.6 1. modifed hold fgure and description p15 oct/22/2014 2. modifed notes for sfdp table p29 1.7 1. updated block diagram p9 ma y/14/2015 2. updated package outline diagram for wson 8l p56 1.8 1. revised hold feature descriptions p15 jun/04/2015 2. modifed copyright years p60 p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e 60 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2009~2015. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com p/n: pm1548 rev. 1.8, jun 04, 2015 mx25l1606e |
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